Robert, thanks for the quick reply.
I guess what I was looking for is some kind of validation that my observed combined shift is a reasonable observation, and that correcting is justified. Even if I knew the exact phase shift of the two inductive components, as you point out, the shift in the CT varies with current. So my goal would be to mitigate a 10-20deg shift down to around 1-2deg so as to achieve an overall accuracy within 2%.
Dealing with the shift in software is pretty easy. Turns out that the limiting factor in acquiring the sample pairs is the SPI implementation in the ESP. The actual data rate at 2Mhz is what you would expect at 1Mhz. So there’s plenty of time available. What I’ve done is to actually save all of the VI pairs in memory for a cycle+, and process them later. With this technique I can actually “slide” the current over the voltage by simply adding a constant to the array subscript. As you point out, since I can sustain the high sample rate, interpolation isn’t necessary.
I measured the AC voltage transformer shift at about 6deg with an oscilloscope using a voltage divider on the actual AC line and the output of the transformer. The AC line crossed zero about 280us after the transformer output, so I interpret that as a 6deg leading shift (60Hz). So the CT must shift in the opposite direction 8deg when I observe a 14deg combined shift. My question is why does the AC transformer lead and the CT lag? (I may have that terminology backwards, so straighten me out). [quote=“Robert.Wall, post:3, topic:1692”]
What is rms power? There is average power, but rms power is meaningless. I think you meant apparent power (VA).
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You’re right. I was loosely calling the product of RMS voltage and RMS current RMS power. I’ll try to stick with apparent power.
Looking at it with an oscilloscope, the AC signal before the uncoupling transformer seems to be OK, and my intention was to use that for the voltage samples. You are right in that the uncoupling transformer output is both phase shifted and distorted, so I would use that for the power supply. Actually, there isn’t much of a downside to just staying with an external switching 5V power adapter.
What you see in the picture is 1V + 14I. There’s one unused channel on the second ADC. The standard size PC board would only accommodate 14 CT plugs. But you’re right in that another voltage input could easily be configured to the unused channel.
I seem to recall that a third phase can be derived electrically from the other two, so I assume that could be done mathematically as well, but it would probably be easier to just go with 3V - 13I for a three phase monitor. The way this device is scaled, you could add any number of additional boards for more CTs. I’ve run mine with 28 CTs - no problem. The phasing might become more of an issue though with three phase voltage sensing and three CTs. If you want to pursue this, I think that with a fast processor like the ESP, it’s possible to roll your own SPI with an external clock and to read three ADC’s simultaneously. SPI has discrete MISO lines. I’ve explored this a little as a way to read the voltage and current simultaneously with the previously mentioned extra voltage sensor on the unused channel of the second ADC. I was also looking at a more expensive 12 bit ADC ($7) that can be set up to read any of the inputs quickly into a FIFO.
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