I’ve been exploring the EmonLib library, specifically its use of a low-pass filter for measuring DC offset. While researching, I came across EmonLibCM, which appears to use a different approach for offset removal. I’ve reviewed the documentation on digital filters for offset removal Digital filters for offset removal but would like some clarity on the following:
Best Filter for Offset Removal: Based on your experience, which offset removal method generally provides the best results in practice? Are there particular scenarios where one filter type outperforms others?
Offset Removal Filter in EmonLibCM: Could someone clarify which filter EmonLibCM uses for DC offset removal? How does it compare in performance to the low-pass filter used in EmonLib for this purpose?
Offset Removal for Unsymmetrical Waveforms: In cases where the load causes an asymmetrical waveform (e.g., an incandescent bulb connected in series with a diode), which offset removal method would handle this best? Is there a way to ensure accurate readings with such loads?
Any insights or recommendations would be greatly appreciated!
Answering this one first, you are faced with exactly the same problem that designers faced in the days of analogue television. There they used a known value - the amplitude of the sync pulses - to be able to set the d.c. level which defined “black”. Unless you can do the same, that is, you know beforehand the shape (and generally something particular about the amplitude), there’s nothing you can do about it because of course your current or voltage transformer is inherently a high pass filter. Your underlying problem is, you should not be using half-wave rectification in the first place, except for insignificantly small loads. A large d.c. component will at some point damage any upstream distribution transformer.
You can always download the library and read the code! If you do, you’ll see it calculates the average value over the reporting period and then subtracts this from the rms value. The principal advantage is it does not require time to settle at switch-on, and of course it has in effect a very long time constant.
EmonLib is obsolescent, I have no information as to whether it will ever be withdrawn, but no work has been done on it for several years and I’m not aware that any is envisaged.
Thanks for the reply. How about using an op-amp as suggested in the Improving the quality of the bias source? But instead of using a voltage divider for the non-inverting terminal, it could be directly connected to either a DAC or PWM pin of the MCU, or to a precision voltage reference. I’ve seen some meters where the non-inverting terminal is connected directly to an MCU pin. This approach could provide a more accurate and stable DC bias, as the exact bias voltage would be known and controlled in advance.
However, I’m concerned that if the non-inverting terminal is connected to an MCU pin, the ADC pin of the MCU might experience a temporary negative voltage at power-up, before the MCU can output the required voltage level.
But you’re missing the point. The current transformer has already removed the d.c, long before it hits any electronics. Unless you know where the d.c. level should be on the waveform that comes out of the transformer, you can never restore it. Your only solution is to use a shunt to measure the current, and this brings with it inherent dangers - all the low voltage measurement circuitry is live to the supply, and is something we strongly recommend you do not do, for your safety and the safety of anyone else who might become involved.
No, I am referring to the DC bias voltage applied to center the AC waveform from the current transformer (CT) at VCC/2, which must be manually removed in software before performing RMS calculations.
You’d conflated two problems, you mentioned a half-wave rectified load, so that’s what I was considering. Removing the deliberately applied d.c. bias is a very simple matter, by far the easiest is to measure it! But this costs you an ADC channel (if you have a common bias supply) or use an ADC with differential inputs if the bias supply is derived for each channel separately. Or do as emonLib does and accept the startup problem, or do as emonLibCM does. Using a low impedance common bias voltage means there should be negligible ripple remaining in the bias voltage, which is my preferred choice. As with all engineering, it’s a matter of balance between a number of conflicting requirements.
I’m concerned about the accuracy of DC offset removal techniques, such as using a mean calculation, low-pass filter, or high-pass filter, particularly when the output waveform from a current transformer (CT) is asymmetrical due to various load types. For symmetrical waveforms, these techniques typically produce accurate offset values; for instance, taking the mean offset by averaging samples (offset = ∑(V)/No of samples) or using a low-pass filter often yields an offset near the actual VDD/2, e.g., 1.65V for a 3.3V system.
However, certain loads, such as switching power supplies, cause significant waveform distortion by drawing current in short bursts rather than consistently across the cycle. This results in a non-sinusoidal waveform on the mains current. In such cases, these techniques may yield a DC offset calculation that deviates from the true offset due to the asymmetry in the waveform. Do you think these methods are suitable for handling such distortions, or would you suggest alternative approaches for accurate DC offset determination under these conditions?
How did you arrive at the lower of those two diagrams? What are you trying to illustrate there? Can you explain a little more carefully, because there are two mechanisms acting in series that determine how the actual current wave differs from the input to the ADC, and I think it’s not clear to you what those are and the how their separate effects combine to produce the final wave shape seen at the ADC input.
The distortion won’t typically introduce an offset. Those SMPSs work on a half-cycle basis and are agnostic to whether the half-cycle is positive or negative. So in steady state conditions the negative half-cycle is a mirror image of the positive half-cycle. You can see some examples in this post and the one immediately following it. That third one has the raw data attached if you want to play with it in a spreadsheet.
In the case where the load being supplied by the SMPS is very variable then you have the situation where no two half-cycles are the same. You can somewhat see that in the first trace of those three: the second positive peak is bigger than all the rest. You might be tempted to say “ah huh… that signal has a positive bias and is introducing a DC offset” but I’m sure if I panned out we’d see just as many on the negative side.
But, even if there was something in the power supply design that only happened every other half cycle and so introduced a bias, you’re then back to (or at least approaching) a classic half-wave rectified load. A cheap hair-dryer on low setting is a good example of that. That DC offset can’t get through the CT. So while the signal might not be balanced around 0 on the primary side of the CT it will be on the secondary side. As @Robert.Wall says above, that DC offset is permanently lost to anything on the secondary side of the CT (like your ADC) and there is no way of recreating it in order to measure it. It’s an easy experiment to try for yourself if you have a hair-dryer, a CT and a scope.
