Correct, when measuring voltage the current will be 10-15mA at most, however when balancing then the voltage drop will affect the whole module not just taking voltage readings.
So the voltage on the ATTINY chip will be bouncing up and down hundreds of times per second (because its driving a PWM output to the MOSFET). We already know that the ATTINY doesn’t regulate its internal clock very well when exposed to voltage changes, so that in turn will affect the communications to other modules.
Additionally, the voltage drop may push the ATTINY into brown out detection, which causes the ATTINY to reboot.
Its there any problem running 5 wires to the 4 modules (13.8v LFP)? Wiring would be like this:
Negative of Cell 1 to Negative of module 1
Positive of cell 1 to Positive of module 1 and Negative of module 2
Positive of cell 2 to Positive of module 2 and Negative of module 3
Positive of cell 3 to Positive of module 3 and Negative of module 4
Positive of cell 4 to Positive of module 4
I can’t see an issue with this. The cells are wired with the bus bars this way anyway, so those connections are going to be joined.
edit: wrote negative instead of positive for module 4
Someone posted above that did this and discovered that when one cell is doing bypass the neighboring cells can get goofy voltage readings and go into bypass too. If you have fat and short enough wires, it should not make a difference, but if you use the wires that come with the jcl connectors that will be a bit thin.
I recommend putting the balancing modules as near to the cells as possible, connect directly to the cells if possible. This makes it easy to isolate and identify which module belongs to what cell etc. shorter cable paths also reduce resistance.
