Has the YHDC SCT-013-000 Current Transformer (or any other CT) been tested during a bolted fault on the circuit it is monitoring? Specifically, during a bolted fault (meaning the hot and neutral are directly connected in a short circuit - this is the worst-case, highest current fault), what is the resulting maximum voltage that will be seen at the input to the ADC, and what is the risk of blowing the ADC/PI/Arduino under this condition?
Suppose I’m monitoring a 20A circuit and I have my burden resistor set to give me 4.5 V peak-to-peak at 20A. Rule-of-thumb, during a fault the breaker will trip at 15x breaker rating, or 300A, or a peak-to-peak as seen at the ADC of more than 60 volts.
I presume the CT will saturate and the actual maximum voltage will never reach this high level, but how high can it get? How much voltage can the ADC take before it is destroyed? Is there an effective surge protection that can be used, perhaps a series cap or inductor to ground?
This is a question that I looked at several years ago (and yes, we too use the term ‘bolted fault’).
Have you looked at the saturation curve in the test report? There’s been a lot of discussion about the current that the input protection can tolerate, which is not so clearly defined in the data sheet as the voltage is. The inclusion of the series resistor in later versions of the emonTx is intended to reduce the risk of damage to the input protection.
To fully evaluate the input design under those conditions, a complete and accurate mathematical model of the c.t. is needed, and, to the best of my knowledge, that’s not available.
I came to the conclusion that the impedance of the bias circuit in conjunction with the saturation of the c.t. would probably, but not definitely, be sufficient to prevent major damage. Having said that, I’m not aware of a report of the processor being damaged, so that conclusion appears to have been valid.
And one more point, the “Rule-of-thumb, during a fault the breaker will trip at 15x breaker rating, or 300A” isn’t a valid starting point. That is the current at which the breaker clears in a defined time. What you need is the PSC - Prospective Short-circuit Current - which will be set by the fault level of your supply, which includes things like the length, hence impedance, of your feeders from the final distribution transformer, the size and impedance of that transformer, and even the stiffness of the supply feeding it.
Thanks. I did look at the saturation curve, but I don’t know if that is applicable under fault conditions during such a high rate of change. I also don’t have the bandwidth to develop a full mathematical/theoretical model. I am considering just doing a test… set up a situation where I can safely generate a fault while tracking it with an inexpensive ADC and see what results. If I do this (and that’s a big “if”), I’ll post the results here. Regarding the 15x rule, granted it is an approximation, but that’s all I need to illustrate the point here.
For the moment, I’ll be content with your note about no reported instances of fault damage and assume that the ct saturation and circuit impedance will be protection enough.
My point about the circuit breaker is the let-through current will be a lot higher than the tripping current on the I2t curve, so a lot worse than you were assuming.
You can estimate it with a simple measurement: measure your line voltage, apply a large load (as large as you can) and measure the dip in voltage. Then from that, the voltage and the load resistance, you can calculate the impedance of the supply. It will not be accurate, but it will be a reasonable guide.