There’s a picture of how long it takes to read the scratchpad relative to a mains cycle here.
The typical bit-banging OneWire librarires sit in a busy loop with interrupts disabled for:
. 70 usecs for the initial reset pulse
. 10 usecs to write a ‘1’ bit
. 65 usecs to write a ‘0’ bit
. 13 usecs to read a bit
then you can take as long as you like before you do the next bit. I’m not sure what speed you run the ADC at, but if it’s at 110 usecs, then I’d expect some lost interrupts during the 480 usecs reset pulse (which starts each one wire transaction - but only once at the beginning of the entire transaction, you can see it in the scope trace above).
If you offload it all to a uart as per Tutorial 214 then there’s no timing critical bits for the cpu at all, and interrupts are never disabled to do OneWire transactions.