inspired by the new v4,I have decided to start working on a possible V5.
I have re-created the PCB to add Active Balancing using the Inductive process.
I have decided to use the ETA3000 chip, but it would have been quite cool to directly use the uC to handle the buck/boost circuit. (Unfortunetly the ATTiny don’t have enough RAM and IO to do also that. I had a demo/draft done by a ATMega, but in such case there are a lot of other issues/limitations. So a proper dedicated chip is easier to handle)
My board uses mostly all parts available at JLCPCB SMT assemply line, so the board could also be assembled directly during PCB manufacturing. Unfortunately the uC, the reference and the JST connectors must be soldered separately!
Anyway, I’m completely rewriting the software on the CellModule, I have unfortunately broken the v4 Protocol due to the fact that that I use a 16bit address, and I have made a lot of other changes. (This should also allow more that 16 modules in the chain/on the same bank)
My initial firmware idea was to use a Scheduler to handle all the tasks, but the low SRAM on the ATTiny doesn’t allow it. I was looking for an alternative parts with more SRAM but at that point a ATMega328p would be cheaper.
I have uploaded the sources of both the PCB and the firmware.
Please keep in mind that this is a Work in Progress project and things could change!
Unfortunately I’m an Altium guy so the project has been created with it.
Any suggestions/ideas are welcome!